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PCF2113x
LCD controllers/drivers
Rev. 04 -- 4 March 2008 Product data sheet
1. General description
The PCF2113x is a low-power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 lines of 12 characters or 1 line of 24 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter `x' in PCF2113x characterizes the built-in character set. Various character sets can be manufactured on request.
2. Features
I Single-chip LCD controller/driver I 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons I 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese) and user-defined symbols I Icon mode for e.g. additional segment display section: reduced current consumption while displaying icons only I Icon blink function I Very low current consumption (20 A to 200 A): N Icon mode: < 25 A N Power-down mode: < 2 A I On-chip: N Configurable 4, 3 or 2 voltage multiplier, generating LCD supply voltage VLCD, independent of VDD, programmable by instruction (external supply also possible) N Temperature compensation of on-chip generated VLCD: -0.16 %/K to -0.24 %/K (programmable by instruction) N Generation of intermediate LCD bias voltages N Oscillator requires no external components (external clock also possible) I Display data RAM: 80 characters I Character generator ROM: 240 characters of 5 x 8 dots I Character generator RAM: 16 characters of 5 x 8 dots; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application I 4-bit or 8-bit parallel bus and 2-wire I2C-bus interface I 18 row and 60 column outputs
NXP Semiconductors
PCF2113x
LCD controllers/drivers
I Multiplex rates (MUX) 1:18 (for normal operation), 1:9 (for single-line operation) and 1:2 (for Icon-only mode) I Uses common 11 code instruction set (extended) I Logic supply voltage range VDD1 - VSS1 = 1.8 V to 5.5 V (chip may be driven with two battery cells) I VLCD generator supply voltage range VDD2 - VSS2 = 2.2 V to 4.0 V I Display supply voltage range VLCD - VSS2 = 2.2 V to 6.5 V I Direct mode to save current consumption for Icon mode and MUX 1:9 (depending on VDD2 and LCD liquid properties) I CMOS compatible I Remark: Icon mode is a way to save current. When only icons are displayed (i.e. only the lower two rows are active), a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD.
3. Applications
I Telecom equipment I Point-of-sale terminals I Portable instruments
4. Ordering information
Table 1. Ordering information Package Name PCF2113AU/10/F4 PCF2113DU/F4 PCF2113DH/4 PCF2113DU/2/F4 PCF2113EU/2/F4 PCF2113WU/2/F4 LQFP100 Description chip on flexible film carrier chip in tray Version Type number
plastic low profile quad flat package; 100 leads; SOT407-1 body 14 x 14 x 1.4 mm chip with bumps in tray chip with bumps in tray chip with bumps in tray -
5. Marking
Table 2. Marking codes Marking code PCF2113DH Type number PCF2113DH/4
PCF2113_FAM_4
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Product data sheet
Rev. 04 -- 4 March 2008
2 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
6. Block diagram
C1 to C60 R1 to R18
60 BIAS VOLTAGE GENERATOR VLCDSENSE VLCD GENERATOR VDD3 COLUMN DRIVERS 60 DATA LATCHES 60 SHIFT REGISTER 5 x 12 BIT 5 CURSOR AND DATA CONTROL 5 VDD1 VDD2 CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS 8 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
18 ROW DRIVERS 18 SHIFT REGISTER 18-BIT
VLCDIN
VLCDOUT
OSCILLATOR
OSC
VSS1 VSS2
TIMING GENERATOR
T1 T2 T3
7
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
PD
PCF2113x
DATA REGISTER (DR) 8 I/O BUFFER 8 BUSY FLAG INSTRUCTION REGISTER (IR) 8 POWER-ON RESET
DB0 to DB3/SA0
DB4 to DB7
E
R/W
RS
SCL
SDA
mge990
Fig 1.
Block diagram of PCF2113x
PCF2113_FAM_4
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Product data sheet
Rev. 04 -- 4 March 2008
3 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
7. Pinning information
7.1 Pinning
96 DB3/SA0
100 VDD2
91 R/W
88 SDA
99 DB0
98 DB1
97 DB2
95 DB4
94 DB5
93 DB6
92 DB7
87 SCL
86 R17
90 RS
85 R1
84 R2
83 R3
82 R4
81 R5
80 R6
79 R7
78 R8
77 C1
VDD1 OSC PD T1 VSS1 VSS2 VLCDOUT VLCDIN R9
1 2 3 4 5 6 7 8 9
76 C2
89 E
75 C3 74 C4 73 C5 72 C6 71 C7 70 C8 69 C9 68 C10 67 C11 66 C12 65 C13 64 C14
R10 10 R11 11 R12 12 R13 13 R14 14 R15 15 R16 16 R18 17 C60 18 C59 19 C58 20 C57 21 C56 22 C55 23 C54 24 C53 25
PCF2113x
63 C15 62 C16 61 C17 60 C18 59 C19 58 C20 57 C21 56 C22 55 C23 54 C24 53 C25 52 C26 51 C27
C52 26
C51 27
C50 28
C49 29
C48 30
C47 31
C46 32
C45 33
C44 34
C43 35
C42 36
C41 37
C40 38
C39 39
C38 40
C37 41
C36 42
C35 43
C34 44
C33 45
C32 46
C31 47
C30 48
C29 49
C28 50
mge989
Fig 2.
Pin configuration for PCF2113DH (LQFP100)
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
4 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
dummy pad 5
71
81
78
77
76
75
74
73
72
70
69
68
67
66
65
64
63
62
61
60
59
58
83
82
80
79
dummy pad 6 C2 C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA
84 85 86 87 88 89 90 91 92 93 94 95 96 97
y
57 56 55 54 53 52 51 50 49
dummy pad 4
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C3
C4
C5
C6
C7
C8
C9
dummy pad 3 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48
PCF2113x
48 47 46 45 44
E 3.36 mm RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD2
98 99 100 101 102 103 104 105 106 107 108 109 0 0
x
43 42 41 40 39 38 37 36 35
34 33 32
C49 C50 C51 C52 dummy pad 2
VDD3 dummy pad 7
110 111 112 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 10 29 dummy pad 1 1 2 3 4 5 6 7 8 9
31 30
VLCDOUT
VDD1
VSS1 VSS2
VLCDSENSE
VLCDIN
OSC
PD
R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59
dummy pad 8
3.52 mm
mgu205
Fig 3.
Bonding pad locations for PCF2113xU (bottom view) Table 3. Pin 1 2 3 4 5 6 7 Pin (LQFP100 package) or pad allocation table Pad 1 2 3 4 5 6 7 8 9 10 Symbol VDD1 OSC PD T3 T1 T2 VSS1 VSS2 VLCDOUT VLCDSENSE Pin 76 77 78 to 85 86 87 88 89 90 91 Pad 84 85 86 87 to 94 95 96 97 98 99 100 Symbol dummy pad C2 C1 R8 to R1 R17 SCL SDA E RS R/W
(c) NXP B.V. 2008. All rights reserved.
PCF2113_FAM_4
Product data sheet
Rev. 04 -- 4 March 2008
C58 C57 C56 C55 C54 C53
T3
T1
T2
5 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
Pin (LQFP100 package) or pad allocation table ...continued Pad 11 12 to 19 20 21 to 28 29 30 31 to 55 56 57 58 to 82 83 Symbol VLCDIN R9 to R16 R18 C60 to C53 dummy pad dummy pad C52 to C28 dummy pad dummy pad C27 to C3 dummy pad Pin 92 93 94 95 96 97 98 99 100 Pad 101 102 103 104 105 106 107 108 109 110 Symbol DB7 DB6 DB5 DB4 DB3/SA0 DB2 DB1 DB0 VDD2 VDD3 -
Table 3. Pin 8 9 to 16 17 18 to 25 26 to 50 51 to 75 Table 4. Pad Type
Bonding pad dimensions Size galvanic pure Au (50 6) x (90 6) x (17.5 5) <2 <5 62 x 100 36 x 76 -635.0 380 25 Fab 1
[1]
Unit m m m m m m m Fab 2 3.47 3.31
[2]
Bump dimensions Height difference in one die Convex deformation Pad size (aluminium) Passivation opening Pad pitch Wafer thickness (excluding bumps) Die size X Die size Y
[1] [2]
3.52 3.36
mm mm
Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer). Fab 2 identification starts with AXnnnn, where X represents a letter or a number and n represents a number between 0 and 9 (6 inch wafer).
Table 5. Pin and bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3). Symbol VDD1 OSC PD T3 T1 T2 VSS1
PCF2113_FAM_4
Pin 1 2 3 4 5
Type P I I I I I P
Pad 1 2 3 4 5 6 7
X (m) -1345 -1155 -1 055 -845 -765 -665 -525
Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550
Description supply voltage 1 for all except VLCD generator oscillator and external clock input power-down select input; for normal operation PD is LOW test pad; open circuit and not user accessible test pin; must be connected to VSS1 test pad; must be connected to VSS1 ground 1 for all except VLCD generator
(c) NXP B.V. 2008. All rights reserved.
[1]
Product data sheet
Rev. 04 -- 4 March 2008
6 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
Table 5. Pin and bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3). Symbol VSS2 VLCDOUT VLCDSENSE VLCDIN R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 dummy pad 1 dummy pad 2 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37
PCF2113_FAM_4
Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
Type P O I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Pad 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
X (m) -455 -295 -145 15 175 245 315 385 455 525 595 665 735 805 875 995 1065 1135 1205 1275 1345 1435 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630
Y (m) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1395 -1255 -1155 -1055 -955 -735 -635 -535 -435 -335 -235 -135 -35 65 165 265 365
Description ground 2 for VLCD generator VLCD output if VLCD is generated internally input (VLCD) for voltage multiplier regulation input for generation of LCD bias levels LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output
(c) NXP B.V. 2008. All rights reserved.
[2] [2][3] [2]
Product data sheet
Rev. 04 -- 4 March 2008
7 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
Table 5. Pin and bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3). Symbol C36 C35 C34 C33 C32 C31 C30 C29 C28 dummy pad 3 dummy pad 4 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 dummy pad 5 dummy pad 6 C2
PCF2113_FAM_4
Pin 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Pad 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
X (m) 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1435 1335 1225 1115 1005 765 665 565 465 365 265 165 65 -35 -135 -235 -335 -435 -535 -635 -735 -835 -965 -1065 -1165 -1265 -1465 -1630 -1630
Y (m) 465 565 665 765 865 965 1065 1165 1265 1335 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1550 1355 1255
Description LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output LCD column driver output
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
8 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
Table 5. Pin and bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3). Symbol C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA E RS R/W DB7 DB6 DB5 DB4 DB3/SA0 DB2 DB1 DB0 VDD2 VDD3 dummy pad 7 dummy pad 8
[1] [2] [3] [4]
Pin 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 -
Type O O O O O O O O O O I I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O P P -
Pad 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
X (m) -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1465
Y (m) 1185 1115 1045 975 905 835 765 695 625 555 375 305 85 -15 -115 -215 -315 -415 -515 -615 -715 -815 -915 -1015 -1235 -1395 -1550
Description LCD column driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output LCD row driver output I2C-bus serial clock input I2C-bus serial data input/output data bus clock input register select input read or write input 8-bit bidirectional bus bit 7 8-bit bidirectional bus bit 6 8-bit bidirectional bus bit 5 8-bit bidirectional bus bit 4 8-bit bidirectional bus bit 3 or I2C-bus address input 8-bit bidirectional bus bit 2 8-bit bidirectional bus bit 1 8-bit bidirectional bus bit 0 supply voltage 2 for VLCD generator supply voltage 3 for VLCD generator [6] [3][6] [4][5] [5] [4] [4] [4]
When the on-chip oscillator is used this pad must be connected to VDD1. When VLCD is generated internally, pins VLCDIN, VLCDOUT and VLCDSENSE must be connected together. When an external VLCD is supplied, this should be done via VLCDIN. In this case only pins VLCDOUT and VLCDSENSE must be connected together. In the LQFP100 version this signal is connected internally and is not accessible. When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode pins DB7 to DB0 must be connected to VDD1 or left open-circuit. When the parallel bus is used, the pins SCL and SDA must be connected to pin VSS1 or pin VDD1; they must not be left open-circuit. When the 4-bit interface is used without reading out from the PCF2113x (bit R/W is set permanently to logic 0), the unused ports DB0 to DB3 can either be connected to VSS1 or VDD1 instead of leaving them open-circuit. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see Table note 4). VDD2 and VDD3 must always be equal.
[5] [6]
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
9 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
8. Functional description
8.1 LCD supply voltage generator
The LCD supply voltage (VLCD) may be generated on-chip. The VLCD generator is controlled by two internal 6-bit registers: VA and VB. Section 10.10.1 shows how to program these registers. The nominal LCD operating voltage at room temperature is given by the relationship: Voper(nom) = (integer value of register x 0.08 V) + 1.82 V With a programmed value from 1 to 63, Voper(nom) = 1.90 V to 6.86 V at Tamb = 27 C. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD tolerance and temperature coefficient must be taken into account. Values below 2.2 V are below the specified operating range of the chip and therefore are not allowed. Value 0 for VA and VB switches off the generator (i.e. VA = 0 in Character mode, VB = 0 in Icon mode). Usually register VA is programmed with the voltage for Character mode and register VB with the voltage for Icon mode. When VLCD is generated on-chip, the VLCD pins must be decoupled to VSS with a suitable capacitor. The generated VLCD is independent of VDD and is temperature compensated. When the VLCD generator and the Direct mode are switched off, an external voltage may be supplied at pins VLCDIN and VLCDOUT (which are connected together). VLCDIN and VLCDOUT may be higher or lower than VDD2. During Direct mode (program DM bit) the internal VLCD generator is turned off and the VLCDOUT output voltage is directly connected to VDD2. This reduces the current consumption during Icon mode and MUX 1:9 (depending on VDD2 and LCD liquid properties). The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to 4 V), the required peak operating voltage of 6.5 V can be generated at any time.
8.2 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1:18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 6. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate.
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
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NXP Semiconductors
PCF2113x
LCD controllers/drivers
Bias levels as a function of multiplex rate Number of levels 5 5 4 Bias voltages[1] V1 VLCD VLCD VLCD V2
3 4 3 4 2 3
Table 6. Multiplex rate 1:18 1:9 1:2
[1]
V3
1 2 1 2 2 3
V4
1 2 1 2 1 3
V5
1 4 1 4 1 3
V6 VSS VSS VSS
The values in the table are given relative to VLCD - VSS, e.g. 34 means {34 x (VLCD - VSS)} + VSS.
8.3 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD1.
8.4 External clock
If an external clock is to be used, this input is at the OSC pin. The resulting display frame f osc frequency is given by: f fr ( LCD ) = ----------3072 Only in the Power-down mode is the clock allowed to be stopped (pin OSC connected to VSS), otherwise the LCD is frozen in a DC state.
8.5 Power-on reset
The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 oscillator cycles to be executed.
8.6 Registers
The PCF2113x has two 8-bit registers: an Instruction Register (IR) and a Data Register (DR). The Register Select (RS) signal determines which register will be accessed. The instruction register stores instruction codes such as `display clear', `cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to but not read from by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `read data' instruction.
8.7 Busy flag
The busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions must only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles.
PCF2113_FAM_4
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Product data sheet
Rev. 04 -- 4 March 2008
11 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
8.8 Address counter
The Address Counter (AC) assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands `set DDRAM address' and `set CGRAM address'. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when bit RS = 0 and bit R/W = 1.
8.9 Display data RAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Figure 4. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00h in line 1 are displayed. Figure 5 and Figure 6 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 7.
display position DDRAM address
non-displayed DDRAM addresses 12345
00 01 02 03 04
22 23 24
15 16 17 18 19 4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345
00 01 02 03 04
10 11 12
09 0A 0B 0C 0D 24 25 26 27
line 1
DDRAM address
12345
40 41 42 43 44
10 11 12
49 4A 4B 4C 4D 64 65 66 67
line 2
2-line display
mge991
Fig 4.
DDRAM to display mapping: no shift
display position DDRAM address
1
23
4
5
22 23 24
14 15 16
4F 00 01 02 03
1-line display 1 DDRAM address 23 4 5 10 11 12
08 09 0A
27 00 01 02 03
line 1
1
23
4
5
10 11 12
48 49 4A
67 40 41 42 43
line 2
2-line display
mge992
Fig 5.
DDRAM to display mapping: right shift
PCF2113_FAM_4
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Product data sheet
Rev. 04 -- 4 March 2008
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NXP Semiconductors
PCF2113x
LCD controllers/drivers
display position DDRAM address
1
23
4
5
22 23 24
16 17 18
01 02 03 04 05
1-line display 1 DDRAM address 23 4 5 10 11 12
0A 0B 0C
01 02 03 04 05
line 1
1
23
4
5
10 11 12
4A 4B 4C
41 42 43 44 45
line 2
2-line display
mge993
Fig 6. Table 7. Mode
DDRAM to display mapping: left shift Address space and wrap-around operation 1 x 24 00h to 4Fh 4Fh to 00h 2 x 12 00h to 27h; 40h to 67h 27h to 40h; 67h to 00h 27h to 00h; 67h to 40h 1 x 12 00h to 27h 27h to 00h 27h to 00h
Address space Read/write wrap-around (moves to next line)
Display shift wrap-around 4Fh to 00h (stays within line)
8.10 Character generator ROM
The Character Generator ROM (CGROM) generates 240 character patterns in a 5 x 8 dot format from 8-bit character codes. Figure 7, Figure 8, Figure 9 and Figure 10 show the character sets that are currently implemented.
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
13 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mlb245
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 7.
Character set `A' in CGROM
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
14 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgd688
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 8.
Character set `D' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgd689
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 9.
Character set `E' in CGROM
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lower 4 bits xxxx
upper 4 bits 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
mgu204
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 10. Character set `W' in CGROM
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8.11 Character generator RAM
Up to 16 user-defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Figure 18 and Figure 19) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Figure 7, Figure 8, Figure 9 and Figure 10). Figure 11 shows the addressing principle for the CGRAM.
character codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
mge995
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logic OR with the cursor. Data in the 8th position appears in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' command. Bit 6 can be set using the `set DDRAM address' command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag' and `address counter' command.
Fig 11. Relationship between CGRAM addresses, data and display patterns
8.12 Cursor control circuit
The cursor control circuit generates the cursor underline and/or cursor blink as shown in Figure 12 at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited.
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cursor 5 x 7 dot character font alternating display
mga801
Cursor display example Fig 12. Cursor and blink display examples
Blink display example
icon 1 row 17
icon 5
row 8
row 2
row 1 cursor
001aah687
Bit Q = 1
Fig 13. Example of a display with icons
8.13 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.
8.14 LCD row and column drivers
The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figure 14, Figure 15, Figure 16 and Figure 17 show typical waveforms. Unused outputs should be left unconnected.
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frame n VLCD V2 ROW 1 V3/V4 V5 VSS
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5 R6 R7 R8 R17
VLCD V2 ROW 17 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 COL 1 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS Voper 0.5Voper 0.25Voper state 1 0 V -0.25Voper -0.5Voper -Voper
ROW 2
COL 2
Voper 0.5Voper 0.25Voper state 2 0 V -0.25Voper -0.5Voper -Voper
1 2 3 9 1 2 3 9
mgu217
R9 to R16 and R18 to be left open
Fig 14. MUX 1:9 LCD waveforms; Character mode
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frame n VLCD V2 ROW 1 V3/V4 V5 VSS VLCD V2 ROW 9
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5 R6 R7 R8 R9
V3/V4 V5 VSS
VLCD V2 V3/V4 V5 VSS VLCD V2
ROW 2
COL 1
V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS Voper
COL 2
0.5Voper 0.25Voper state 1 0 V -0.25Voper -0.5Voper -Voper
Voper 0.5Voper 0.25Voper state 2 0 V -0.25Voper -0.5Voper -Voper
123 18 1 2 3 18
mge996
Fig 15. MUX 1:18 LCD waveforms; Character mode
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frame n
frame n + 1 only icons are driven (MUX 1:2)
VLCD ROW 17 2/3 1/3 VSS
VLCD ROW 18 2/3 1/3 VSS
VLCD ROW 1 to 16 2/3 1/3 VSS
VLCD COL 1 ON/OFF 2/3 1/3 VSS
VLCD COL 2 OFF/ON 2/3 1/3 VSS
VLCD COL 3 ON/ON 2/3 1/3 VSS
VLCD COL 4 OFF/OFF 2/3 1/3 VSS
mge997
Fig 16. MUX 1:2 LCD waveforms; Icon mode (a)
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frame n
frame n + 1 state 1 (ON)
state 1 COL 1 - ROW 17
Voper 2/3Voper 1/3Voper 0 -1/3Voper -2/3Voper -Voper Voper
state 2 (OFF)
R17 R18 R1-16
state 3 (OFF)
state 2 COL 2 - ROW 17
2/3Voper 1/3Voper 0 -1/3Voper -2/3Voper -Voper Voper 2/3Voper 1/3Voper
state 3 COL 1 - 0 ROW 1 to 16 -1/3Voper -2/3Voper -Voper
mge998
Von(RMS) = 0.745Voper Voff(RMS) = 0.333Voper
V on D = --------- = 2.23 V off Fig 17. MUX 1:2 LCD waveforms; Icon mode (b)
8.15 Power-down mode
The chip can be put into Power-down mode by applying an external HIGH level to the PD pin. In Power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked.
8.16 Reset function
The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, including a `clear display', requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 8.
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State after reset Control bit state I/D = 1 S=0 D=0 C=0 B=0 Conditions +1 (increment) no shift display off cursor off cursor character blink off 8-bit interface 1-line display normal instruction set MUX 1:18 mode
Table 8. Step 1 2 3
Function clear display entry mode set display control
4
function set
DL = 1 M=0 H=0 SL = 0
5
default address pointer the Busy Flag (BF) indicates the busy state lasts 2 ms; the chip to DDRAM the busy state (BF = 1) until may also be initialized by software; initialization ends see Table 26 (8-bit interface) and Table 27 (4-bit interface). icon control display or screen configuration VLCD temperature coefficient set VLCD I2C-bus interface reset S1 = 1; S0 = 0 VLCD generator voltage multiplier set at factor 4 set HVgen stages IM = 0; IB = 0; DM = 0 L = 0; P = 0; Q = 0 TC1 = 0; TC2 = 0 VA = 0; VB = 0 icons, icon blink and Direct mode disabled default configurations default temperature coefficient VLCD generator off
6 7 8 9 10 11
9. Instructions
Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR), can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs. The instruction set for I2C-bus commands is given in Table 9. Section 11.2.1 discusses how these control and command bytes are embedded in the I2C-bus protocol.
Table 9. Instruction set for I2C-bus commands Control byte Co[2] RS 0 0 0 0 0 0 Command byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 I2C-bus commands
[1]
I2C-bus commands
[1]
[1] [2]
R/W is set together with the slave address. For explanation, see Table 11.
The PCF2113x operation is controlled by the instructions shown in Table 10 together with their execution time. Details are explained in subsequent sections.
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There are 4 types of instructions:
* * * *
Designate PCF2113x functions such as display format, data length Set internal RAM addresses Perform data transfer with internal RAM Other functions
In normal use, data transfer instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the `read busy flag' and `read address' instructions will be executed. Because the busy flag is set to logic 1 while an instruction is being executed, check to ensure it is logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 10. An instruction sent while the busy flag is logic 1 will not be executed.
Table 10. Instruction set with parallel bus commands Control and command bits RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description[1] Required clock cycles 3 3
Instruction
H = 0 or 1 (basic and extended functions) NOP Function set 0 0 0 0 0 0 0 0 0 1 0 DL 0 0 0 M 0 SL 0 H no operation sets interface Data Length (DL), number of display lines (M), single line/MUX 1:9 (SL) and extended instruction set control (H) reads the Busy Flag (BF), indicating internal operating is being performed, and the Address Counter (AC) reads data from CGRAM or DDRAM writes data to CGRAM or DDRAM 0 0 0 0 0 1
Read busy flag and address counter Read data Write data
0
1
BF
AC
0
1 1
1 0
read data write data
3 3
H = 0 (basic functions) Clear display 0 0 0 0 clears entire display and sets 165 DDRAM address 0 in address counter sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged 3
Return home
0
0
0
0
0
0
0
0
1
0
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Table 10.
Instruction set with parallel bus commands ...continued Control and command bits RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S Description[1] Required clock cycles
Instruction
Entry mode set
0
3 sets cursor move direction (I/D) and specifies shift of display (S); these operations are performed during data write and read sets entire display on/off (D), 3 cursor on/off (C) and blink of cursor position character (B) moves cursor or shifts display (S/C) to right or left (R/L) without changing the DDRAM contents 3
Display control
0
0
0
0
0
0
1
D
C
B
Cursor/display shift
0
0
0
0
0
1
S/C
R/L
0
0
Set CGRAM address
0
0
0
1
ACG
3 sets CGRAM address; bit DB6 is to be set by the command `set DDRAM address'; the descriptions of the commands provide details sets DDRAM address 3
Set DDRAM address Reserved Screen configuration Display configuration Icon control Temperature control Set HVgen stages
0
0
1
ADD
H = 1 (extended functions) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 IM 0 0 0 1 P IB 1 L Q DM do not use set screen configuration (L) set display configuration, columns (P) and rows (Q) set Icon mode (IM), icon blink (IB), Direct mode (DM) 3 3 3 3 3
TC1 TC2 set temperature coefficient (TC1 and TC2) S1 S0 set internal VLCD generator voltage multiplier stages (S1 = 1 and S0 = 1 are not allowed) store VLCD in register VA or in register VB (V)
Set VLCD
0
0
1
V
voltage
3
[1]
For explanation of symbols, see Table 11.
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Explanation of symbols Logic 0 last control byte select instruction register data length: 4 bits 1 line x 24 character display MUX 1:18 (1 line x 24 character or 2 line x 12 character display) use basic instruction set decrement display freeze display off cursor off cursor character blink off; character at cursor position does not blink cursor move left shift left/right screen; standard connection 1st 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 1 to 60 Logic 1 another control byte follows after data/command select data register data length: 8 bits 2 line x 12 character display MUX 1:9 (1 line x 12 character display) use extended instruction set increment display shift display on cursor on cursor character blink on; character at cursor position blinks display shift right shift left/right screen; mirrored connection 1st 12 characters of 24; columns are from 60 to 1 2nd 12 characters of 24; columns are from 60 to 1 column data; right to left; column data is displayed from 60 to 1
Table 11. Bit Co RS DL
M (no impact if SL = 1) SL H I/D S D C B
S/C R/L L (no impact if M = 1 or SL = 1)
P Q
column data; left to right; column data is displayed from 1 to 60
row data; top to bottom; row data row data; top to bottom; row data is displayed from 1 to 16 and icon is displayed from 16 to 1 and icon row data is in 17 and 18 row data is in 18 and 17 Character mode; full display icon blink disabled Direct mode disabled set VA Icon mode; only icons displayed icon blink enabled Direct mode enabled set VB
IM IB DM V
9.1 Clear display
`Clear display' writes character code 20h into all DDRAM addresses (the character pattern for character code 20h must be a blank pattern), sets the DDRAM address counter to 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction `clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications.
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9.2 Return home
`Return home' sets the DDRAM address counter to 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.
9.3 Entry mode set
9.3.1 Bit I/D
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed.
9.3.2 Bit S
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift.
9.4 Display control (and partial Power-down mode)
9.4.1 Bit D
The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D = 1. When the display is off (D = 0) the chip is in partial Power-down mode:
* The LCD outputs are connected to VSS * The LCD generator and bias generator are turned off
Three oscillator cycles are required after sending the `display off' instruction to ensure all outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running during partial Power-down mode (`display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (pin OSC = VSS). To ensure IDD < 1 A, pin PD and the parallel bus pins DB7 to DB0 should be connected to VDD, pins RS and R/W to VDD or left open-circuit. Recovery from Power-down mode: connect pin PD back to VSS, if necessary pin OSC back to VDD and send a `display control' instruction with D = 1.
9.4.2 Bit C
The cursor is displayed when C = 1 and inhibited when C = 0. The cursor is displayed using 5 dots in the 8th line (see Figure 12). Even if the cursor disappears, the display functions like I/D, remain in operation during display data write.
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9.4.3 Bit B
The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of f osc approximately 1 s, with f blink = ----------------- Hz. 104448 The cursor underline and the cursor character blink can be set to display simultaneously.
9.5 Cursor or display shift
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor display shift'.
9.6 Function set
9.6.1 Bit DL (parallel mode only)
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first `function set' instruction after power-on M, SL and H are set to logic 1. A second `function set' must then be sent (2 nibbles) to set M, SL and H to their required values. `Function set' from the I2C-bus interface sets the DL bit to logic 1.
9.6.2 Bit M
Selects either 1 line x 24 character display (M = 0) or 2 line x 12 character display (M = 1).
9.6.3 Bit SL
Selects MUX 1:9, 1 line x 12 character display (independent of M and L). Only rows 1 to 8 and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2 line x 12 character display mode, however, the second line is not displayed.
9.6.4 Bit H
When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons, as shown in Section 10.
9.7 Set CGRAM address
`Set CGRAM address' writes bits DB5 to DB0 of the CGRAM address ACG into the address counter (A5h to A0h). Data can then be written to or read from the CGRAM.
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Remark: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (A6h to A0h). With the `set CGRAM address' command, only bits DB5 to DB0 are set. Bit DB6 can be set using the `set DDRAM address' command first, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can be read using the `read busy flag' and `read address' command. When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not set (e.g. by an earlier DDRAM write or read action).
9.8 Set DDRAM address
`Set DDRAM address' writes the DDRAM address ADD into the address counter (A6h to A0h). Data can then be written to or read from the DDRAM.
9.9 Read busy flag and read address
`Read busy flag and address counter' reads the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed. At the same time, the value of the address counter (A6h to A0h) is read out, into DB6 to DB0. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM
`Write data' writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `set CGRAM address' or `set DDRAM address' command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are `not relevant'.
9.11 Read data from CGRAM or DDRAM
`Read data' reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM. The most recent `set address' command determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. There are only three instructions that update the DR:
* `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM
Other instructions (e.g. `write data', `cursor/display shift', `clear display' and `return home') do not modify the data register content.
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10. Extended function set instructions and features
10.1 New instructions
H = 1 sets the chip into Extended instruction set mode.
10.2 Icon control
The PCF2113x can drive up to 120 icons. See Figure 18 and Figure 19 for CGRAM to icon mapping.
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 -
1
2
3
4
5
6
7
8
9
10
56 57 58 59 60
ROW 18 -
61 62 63 64 65
66 67 68 69 70
116 117 118 119 120
mge999
block of 5 columns
Fig 18. CGRAM to icon mapping (a)
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icon no.
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
56-60 61-65
even even
17/56-60 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 0
0 0
1 1
0 1
1 0
1 0
1 1
1 1
1 0
1 0
1 0
116-120 1-5
even odd (blink)
18/56-60 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
0 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
mgg001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig 19. CGRAM to icon mapping (b)
10.3 Bit IM
When IM = 0, the chip is in Character mode. In Character mode, characters and icons are driven (MUX 1:18 or MUX 1:9). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = 1, the chip is in Icon mode. In Icon mode only the icons are driven (MUX 1:2) and the VLCD generator, if used, produces the VLCD voltage as programmed in register VB.
Table 12. IM 0 1 Character/Icon mode operation Mode Character mode Icon mode VLCD defined in VA defined in VB
10.4 Bit IB
Icon blink control is independent of the cursor/character blink function. When IB = 0, the icon blink is disabled. Icon data is stored in CGRAM characters 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). When IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter).
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Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not used (see Table 13). Icon states for the odd phase are stored in CGRAM characters 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters.
Table 13. Parameter Cursor character blink Icons Blink effect for icons and cursor character blink Even phase block (all on) state 1; CGRAM character 0 to 2 Odd phase normal (display character) state 2; CGRAM character 4 to 6
10.5 Direct mode
When DM = 0, the chip is not in the Direct mode. Either the internal VLCD generator or an external voltage may be used to achieve VLCD. When DM = 1, the chip is in Direct mode. The internal VLCD generator is turned off and the output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage). The Direct mode can be used to reduce the current consumption when the required output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in Icon mode or in MUX 1:9 (depending on LCD liquid properties).
10.6 Voltage multiplier control
10.6.1 Bits S1 and S0
A software configurable voltage multiplier is incorporated in the VLCD generator and can be set via the `Set HVgen stages' command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required output voltage VLCD (see Table 14).
Table 14. S1 0 0 1 1 S1 and S0 control of voltage multiplier S0 0 1 0 1 Description set VLCD generator stages to 1 (2 x voltage multiplier) set VLCD generator stages to 2 (3 x voltage multiplier) set VLCD generator stages to 3 (4 x voltage multiplier) do not use
10.7 Screen configuration
10.7.1 Bit L
L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120; default. L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout.
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10.8 Display configuration
10.8.1 Bit P
The P bit is used to flip the display left to right by mirroring the column data, as shown in Figure 20. This allows the display to be viewed from behind instead of front, enhances the flexibility in the assembly of equipment and avoids complicated data manipulation within the controller. P = 0: default. P = 1: mirrors the column data.
0 P= =P 1
P 0= =1 P
001aah714
Fig 20. Use of P bit
10.8.2 Bit Q
The Q bit flips the display top to bottom by mirroring the row data. Q = 0: default. Q = 1: mirrors the row data. A combination of Q and P allows the display to be rotated 180 deg, as shown in Figure 21. This is useful for viewing the display from the opposite edge.
P=0 Q=0 P=1 Q=1
001aah715
Fig 21. Use of P and Q bits
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10.9 Temperature control
Default is bit TC1 = 0 and bit TC2 = 0. Selects the default temperature coefficient for the internally generated VLCD (see Table 15).
Table 15. Bit TC1 0 1 0 1 TC1 and TC2 selection of VLCD temperature coefficient Bit TC2 0 0 1 1 VLCD temperature coefficient TC (typical values) TC = -0.16 %/K TC = -0.18 %/K TC = -0.21 %/K TC = -0.24 %/K
10.10 Set VLCD
The VLCD value is programmed by instruction. Two on-chip registers, VA and VB hold VLCD values for the Character mode and the Icon mode respectively. The generated VLCD is independent of VDD, allowing battery operation of the chip.
10.10.1 VLCD programming
1. Send `function set' instruction with H = 1 2. Send `set VLCD' instruction to write to voltage register: a. If DB[7:6] = 10, then DB[5:0] represents VLCD of Character mode (VA) b. If DB[7:6] = 11, then DB[5:0] represents VLCD of Icon mode (VB) c. DB[5:0] = 00 0000 switches VLCD generator off (when selected) d. During `display off' and power-down the VLCD generator is also disabled 3. Send `function set' instruction with H = 0 to resume normal programming Section 8.1 shows the relation between VLCD and registers VA and VB.
10.11 Reducing current consumption
Reducing current consumption can be achieved by one of the options given in Table 16. When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator.
Table 16. Reducing current consumption Alternative mode Icon mode (control bit M) display off (control bit D) Direct mode Power-down mode (PD pin)
Original mode Character mode Display on VLCD generator operating Any mode
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11. Interfaces to microcontroller
11.1 Parallel interface
The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required (see Section 7). In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the transaction. The higher order bits (corresponding to bits DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (corresponding to bits DB3 to DB0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction: see Figure 22, Figure 23 and Figure 24 for examples of bus protocol. In 4-bit mode, pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
mga804
Fig 22. 4-bit transfer example
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RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
mga805
IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit.
Fig 23. Example of 4-bit data transfer timing sequence
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
mga806
Fig 24. Example of busy flag checking timing sequence
11.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte.
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Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
11.2.1 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2113x read and write cycles is shown in Figure 25, Figure 26 and Figure 27. The slow-down feature of the I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the PCF2113x.
acknowledgement from PCF2113x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
mgg002
S 011101A0 0
PCF2113x slave address
R/W
Fig 25. Master transmits to slave receiver; write mode
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acknowledgement
S
S 0 1 1 1 0 1 A 0 A 1 RSCONTROL BYTE A
0
DATA BYTE
A 0 RSCONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n 0 bytes Co
1 byte
n 0 bytes
acknowledgement
acknowledgement
no acknowledgement
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
mgg003
(1) Last data byte is a dummy byte (may be omitted).
Fig 26. Master reads after setting word address; write word address; set RS; `read data'
acknowledgement from PCF2113x
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
mgg004
Fig 27. Master reads slave immediately after first byte; read mode (RS previously defined)
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 28. System configuration
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SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 29. Bit transfer
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 30. Definition of START and STOP conditions
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 31. Acknowledgement on the I2C-bus
11.2.2 Definitions
* * * * *
Transmitter: the device that sends the data to the bus Receiver: the device that receives the data from the bus Master: the device that initiates and terminates a transfer and generates clock signals Slave: the device addressed by a master Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message control the bus, only one is allowed to do so and the message is not corrupted
* Arbitration: procedure to ensure that if more than one master simultaneously tries to * Synchronization: procedure to synchronize the clock signals of two or more devices
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12. Internal circuitry
Table 17. Symbol VDD1 Device protection circuits Pad 1
VDD1
Internal circuit
VSS1
mgu200
VDD2
109
VDD2
VSS1 VSS2
mgu201
VDD3
110
VDD3
VSS1
mgu202
VSS1 VSS2
7 8
VSS2
VSS1
mgu203
VLCDSENSE VLCDIN VLCDOUT
10 11 9
VSS1
mgu196
SCL SDA
96 97
VDD1
VSS1
mgu198
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Device protection circuits ...continued Pad 2 3 5 6 4 98 99 100 108 to 101 94 to 87 12 to 19 95 20 86 to 85 82 to 58 55 to 31 28 to 21
VSS1
mgu197
Table 17. Symbol OSC PD T1 T2 T3 E RS R/W
Internal circuit
VDD1
VSS1
mgu199
DB0 to DB7 R1 to R8 R9 to R16 R17 R18 C1 to C2 C3 to C27 C28 to C52 C53 to C60
VLCDOUT
13. Limiting values
Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 VDD3 VLCD Vi(n) Vo(n) II IO IDD ISS IDD(LCD) Ptot P/out Vesd Parameter supply voltage 1 supply voltage 2 supply voltage 3 LCD supply voltage voltage on any input voltage on any output input current output current supply current ground supply current LCD supply current total power dissipation power dissipation per output electrostatic discharge voltage HBM MM CDM Ilu Tstg
PCF2113_FAM_4
Conditions logic supply VLCD generator supply analog supply VDD related inputs VLCD related outputs DC level DC level on pins VDD1, VDD2, VDD3 on pins VSS1 and VSS2
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -10 -10 [1] [2] [3] [4]
Max +5.5 +4.0 +4.0 +6.5 +5.5 +6.5 +10 +10 +50 -50 +50 400 100 2000 200 2000 100 +150
Unit V V V V V V mA mA mA mA mA mW mW V V V mA C
-65
latch-up current storage temperature
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[1] [2] [3] [4]
HBM: Human Body Model, according to JESD22-A114. MM: Machine Model, according to JESD22-A115. CDM: Charged-Device Model, according to JESD22-C101. Latch-up testing, according to JESD78.
14. Static characteristics
Table 19. Static characteristics VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD1 VDD2 supply voltage 1 supply voltage 2 logic supply VLCD generator supply; internal VLCD generation (VDD2 and VDD3 < VLCD) analog supply; internal VLCD generation (VDD2 and VDD3 < VLCD)
[1][2] [1]
Parameter
Conditions
Min 1.8 2.2
Typ -
Max 5.5 4.0
Unit V V
VDD3
supply voltage 3
2.2
-
4.0
V
VLCD VPOR ISS
LCD supply voltage power-on reset voltage ground supply current external VLCD; pins VSS1 and VSS2 Character mode; VLCD = 6.5 V; VDD1 = 5.5 V; VDD2 = VDD3 = 4 V Character mode; VLCD = 5 V; VDD1 = VDD2 = VDD3 = 3 V Icon mode; VLCD = 2.5 V; VDD1 = VDD2 = VDD3 = 3 V internal VLCD; pins VSS1 and VSS2 Character mode; VLCD = 6.5 V; VDD1 = 5.5 V; VDD2 = VDD3 = 2.2 V Character mode; VLCD = 5 V; VDD1 = VDD2 = VDD3 = 3 V Icon mode; VLCD = 2.5 V; VDD1 = VDD2 = VDD3 = 2.5 V Power-down mode; VLCD = 2.5 V; VDD1 = VDD2 = VDD3 = 3 V; pins RS, PD, R/W and DB7 to DB0 = HIGH; in OSC = LOW
[4] [4] [3]
2.2 0.9 -
70 45 25
6.5 1.6 120 80 45
V V A A A
[4]
[3][5]
-
190 160 120 2
400 400 5
A A A A
[4]
[3][4]
Logic Vi VIL VIH IL input voltage LOW-level input voltage on pin OSC on any other pin HIGH-level input voltage leakage current on pin OSC on any other pin VI = VDD1 or VSS1 VSS1 - 0.5 VSS1 VSS1 0.7VDD1 -1 VDD1 + 0.5 V VDD1 - 1.2 V 0.3VDD1 VDD1 VDD1 +1 V V V A
VDD1 - 0.1 -
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Table 19. Static characteristics ...continued VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IOL IOH Ipu I2C-bus Input on pins SDA and SCL VI VIL VIH ILI CI IOL(SDA) LCD outputs RO Vbias VLCD output resistance bias voltage variation LCD voltage variation row outputs: pins R1 to R18 column outputs: pins C1 to C60 pins R1 to R18 and C1 to C60 Tamb = 25 C VLCD < 3 V VLCD < 4 V VLCD < 5 V VLCD < 6 V
[1] [2] [3] [4] [5] [6] [7] [8] Spikes on VDD1 or VSS1 which cause (VDD1 - VSS1) 1.6 V can cause a Power-on reset. Resets all logic when VDD1 < VPOR; 3 oscillator cycles required. LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive. Tamb = 25 C; fosc = 200 kHz. LCD outputs are open-circuit; VLCD generator is on; load current IDD(LCD) = 5 A (at VLCD). Tested on a sample basis. Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 A; outputs measured one at a time; external VLCD = 3 V; VDD1 = VDD2 = VDD3 = VLCD. LCD outputs are open-circuit; external VLCD.
[7] [7] [8] [5]
Parameter LOW-level output current HIGH-level output current pull-up current
Conditions VOL = 0.4 V; VDD1 = 5 V VOH = 0.4 V; VDD1 = 5 V VI = VSS1
Min 1.6 -1 0.04
Typ 4 -8 0.15
Max 1
Unit mA mA A
Pins DB7 to DB0
input voltage LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level output current on pin SDA VOL = 0.4 V; VDD1 > 2 V VOL = 0.2VDD1; VDD1 < 2 V VI = VDD1 or VSS1
[6]
VSS1 - 0.5 0 0.7VDD1 -1 3 2 5 10 15 20 -
5.5 0.3VDD1 5.5 +1 30 40 130 160 200 260 340
V V V A pF mA mA k k mV mV mV mV mV
Output on pin SDA
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15. Dynamic characteristics
Table 20. Dynamic characteristics VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified Symbol ffr(LCD) fosc fosc(ext) td(startup)(OSC) tw(pd) tw(spike) Parameter LCD frame frequency oscillator frequency external oscillator frequency start-up delay time on pin OSC power-down pulse width spike pulse width
[3]
Conditions internal clock; VDD = 5.0 V
[1]
Min 45 140 140 1 -
Typ 95 250 200 -
Max 147 450 450 300 90
Unit Hz kHz kHz s s ns
oscillator, after power down on pin PD
[2]
[2]
Timing characteristics of parallel interface tcy(en) tw(en) tsu(A) th(A) tsu(D) th(D) tcy(en) tw(en) tsu(A) th(A) td(DV) th(D) fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA enable cycle time enable pulse width address set-up time address hold time data input set-up time data input hold time enable cycle time enable pulse width address set-up time address hold time data input valid delay time data input hold time I2C-bus interface
Write operation (writing data from microcontroller to PCF2113x); see Figure 32 500 220 50 25 60 25 500 220 50 25 VDD1 > 2.2 V VDD1 > 1.5 V Timing characteristics of
[3];
-
150 250 400 300 300 400 -
ns ns ns ns ns ns ns ns ns ns ns ns ns Hz s s ns ns ns ns pF s s
Read operation (reading data from PCF2113x to microcontroller); see Figure 33
5
see Figure 34 1.3 0.6 100 0
[2][4]
SCL frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line set-up time for a repeated START condition hold time (repeated) START condition
15 + 0.1Cb 15 + 0.1Cb 0.6 0.6
[2][4]
[4]
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Table 20. Dynamic characteristics ...continued VDD1 = 1.8 V to 5.5 V; VDD2 = VDD3 = 2.2 V to 4.0 V; VSS = 0 V; VLCD = 2.2 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified Symbol tSU;STO tSP tBUF Parameter set-up time for STOP condition pulse width of spikes that must on bus be suppressed by the input filter bus free time between a STOP and START condition
Not available at any pin. Tested on a sample basis. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Cb = total capacitance of one bus line in pF.
Conditions
Min 0.6 1.3
Typ -
Max 50 -
Unit s ns s
[1] [2] [3] [4]
RS
VIH VIL
VIH VIL
tsu(A) R/W
th(A)
VIL
VIL
tw(en)
E VIH VIL VIH VIL
th(A)
VIL
tsu(D)
DB0 to DB7 VIH valid data VIL tcy(en)
th(D)
VIH VIL
mbk474
Fig 32. Parallel bus write operation sequence; writing data from microcontroller to PCF2113x
RS
VIH VIL
VIH VIL
tsu(A) R/W
VIH
th(A)
VIH
tw(en)
E VIL VIH VIH VIL
th(A)
VIL
td(DV)
DB0 to DB7 VOH VOL
th(D)
VOH VOL
tcy(en)
mbk475
Fig 33. Parallel bus read operation sequence; writing data from PCF2113x to microcontroller
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SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
t SU;STA t SU;STO
mga728
Fig 34. I2C-bus timing diagram
16. Application information
16.1 Application diagrams
P10 P11 P80CL51 P12
RS R/W E
R17, R18
2
R1 to R16 PCF2113x 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
mgg006
P17 to P14
4
DB7 to DB4
C1 to C60
Fig 35. Direct connection to 8-bit microcontroller; 4-bit bus
P20 P21 P80CL51 P22
RS R/W E
R17, R18
2
R1 to R16 PCF2113x 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
mgg005
P17 to P10
8
DB7 to DB0
C1 to C60
Fig 36. Direct connection to 8-bit microcontroller; 8-bit bus
PCF2113_FAM_4
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PCF2113x
LCD controllers/drivers
OSC VDD
R17, R18
2
VDD R1 to R16
PCF2113x
470 nF 100 nF
16
VLCD C1 to C60 VSS
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS
60
VSS
8
DB7 to DB0 E
RS R/W
mgg007
Fig 37. Typical application using parallel interface
VDD VDD
VDD
OSC VDD
DB3/SA0
R17, R18
2
VDD R1 to R16
PCF2113x
470 nF 100 nF
16
VLCD C1 to C60 VSS SCL SDA
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS
60
VSS
VSS
OSC VDD
DB3/SA0
R17, R18
2
VDD R1 to R16
PCF2113x
470 nF 100 nF
16
VLCD C1 to C60 VSS SCL SDA
1 x 24 CHARACTER LCD DISPLAY PLUS 120 ICONS
60
VSS
SCL SDA
MASTER TRANSMITTER PCF84C81A; P80CL410
mgg008
Fig 38. Application using I2C-bus interface
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16.2 General application information
The required minimum value for the external capacitors in an application with the PCF2113x are: Cext 100 nF between VLCD and VSS, and Cext 470 nF between VDD and VSS. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended Indium Tin Oxide (ITO) track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 for the supply and below 100 for the I/O connections. Higher track resistances reduce performance and increase current consumption. To avoid accidental triggering of power-on reset (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be risen above the specified minimum.
16.3 4-bit operation, 1-line display using internal reset
The program must set functions prior to a 4-bit operation (see Table 21 ). When power is turned on, 8-bit operation is automatically selected and the PCF2113x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 21 step 3). Thus, DB4 to DB7 of the `function set' are written twice.
Table 21. Step 1 2 4-bit operation, 1-line display example using internal reset Display Operation initialized; no display appears sets a 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = VA; 4-bit operation starts from this point and resetting is needed turns on display and cursor; entire display is blank after initialization
Instruction internal power supply on (PCF2113x is initialized by the internal reset) function set RS 0 R/W DB7 DB6 DB5 DB4 0 0 0 1 0
3
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0
5
entry mode set 0 0
sets mode to increment address by 1 and to shift the cursor to the right at the time of write to the DDRAM/CGRAM; display is not shifted P writes 'P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
`write data' to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0
16.4 8-bit operation, 1-line display using internal reset
Table 22 and Table 23 show an example of a 1-line display in 8-bit operation. The PCF2113x functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays
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when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the `return home' operation is performed.
Table 22. Step 1 2 3 4 8-bit operation, 1-line display example; using internal reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialized; no display appears sets to 8-bit operation, selects 1-line display and VLCD = VA turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM/CGRAM; display is not shifted P writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `H' 0 : : 11 12 13 14 15 to 19 20 21 22 23 24 `write data' to CGRAM/DDRAM 1 0 0 1 0
PCF2113_FAM_4
Display
Operation
power supply on (PCF2113x is initialized by the internal reset) function set 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 1 1 0 0 0 display control entry mode set
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
6 7 to 10
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 PH
writes `ILIP' writes `S'
`write data' to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 : : 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS PHILIPS HILIPS entry mode set `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM HILIPS M
sets mode for display shift at time of write writes space writes `M' writes `ICROK' writes `O'
0 0 0 0 0
0 0 0 0 0
1 0 0 1 0
0 0 0 0 0
0 1 1 0 1
1 0 0 0 1
1 0 0 0 1
1 0 0 1 0
1 0 0 1 0
MICROKO MICROKO MICROKO ICROCO MICROCO shifts only the cursor position to the left shifts only the cursor position to the left writes `C' correction; the display moves to the left shifts the display and cursor to the right
(c) NXP B.V. 2008. All rights reserved.
cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM cursor/display shift
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Table 22. Step 25 26 27
8-bit operation, 1-line display example; using internal reset (character set `A') ...continued Instruction RS 0 1 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 shifts only the cursor to the right 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 1 0 MICROCO writes `M' ICROCOM PHILIPS M returns both display and cursor to the original position (address 0) 0 0 0 0 0 0 cursor/display shift `write data' to CGRAM/DDRAM return home Display Operation
Table 23. Step 1 2 3 4
8-bit operation, 1-line display and icon example; using internal reset (character set `A') Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialized; no display appears sets to 8-bit operation, selects 1-line display and VLCD = VA turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM/CGRAM; display is not shifted sets the CGRAM address to position of character `0'; the CGRAM is selected writes data to CGRAM for icon even phase; icon appears power supply on (PCF2113x is initialized by the internal reset) function set 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 1 1 0 0 0 display control entry mode set Display Operation
5
set CGRAM address 0 0 0 1 0 0 0 0 0 0
6 7 8
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 : : sets CGRAM address 0 0 0 1 1 1 0 0 0 0 1 0 1 0
sets the CGRAM address to position of character `0'; the CGRAM is selected writes data to CGRAM for icon odd phase
9 10 11 12 13 14
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 : : function set 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 icon control 0 function set 0 0 set DDRAM address 1 0 1 0
sets H = 1: Extended instruction set icons blink sets H = 0 sets the DDRAM to the first position; DDRAM is selected
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Table 23. Step 15 16 17 22
8-bit operation, 1-line display and icon example; using internal reset (character set `A') ...continued Instruction RS 1 1 R/W 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 1 0 : : return home 0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position (address 0) 0 1 0 0 0 0 0 0 P PH writes `ILIPS' writes `P'; the cursor is incremented by 1 and shifted to the right writes `H' `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM Display Operation
16.5 8-bit operation, 2-line display
For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 24). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other.
Table 24. Step 1 2 3 8-bit operation, 2-line display example; using internal reset Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialized; no display appears sets to 8-bit operation, selects 1-line display and VLCD = VA turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM/CGRAM; display is not shifted P writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `HILIP' writes `S' 1 0 0 0 0 0 1 0 1 0 PHILIPS PHILIPS sets DDRAM to position the cursor at the start of the 2nd line power supply on (PCF2113x is initialized by the internal reset) function set 0 0 4 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 display control Display Operation
entry mode set 0 0 0 0 0 0 0 1 1 0
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
6 to 10 11 12 `write data' to CGRAM/DDRAM 1 0 0 0 0 1 1 1 0 0 sets DDRAM address
: :
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Table 24. Step 13
8-bit operation, 2-line display example; using internal reset ...continued Instruction RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 writes `M' 0 : : `write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 PHILIPS MICROCO sets mode for display shift at the time of write 1 1 0 1 PHILIPS M writes `ICROC' writes `O' 0 1 0 `write data' to CGRAM/DDRAM Display Operation
14 to 18 19
20
entry mode set 0 0 0 0 0 0 0 1 1 1 PHILIPS MICROCO
21
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 1 0 1 HILIPS ICROCOM
writes `M'; display is shifted to the left; the 1st and 2nd lines shift together returns both the display and cursor to the original position (address 0)
22
return home 0 0 0 0 0 0 0 0 1 0 PHILIPS MICROCOM
16.6 I2C-bus operation, 1-line display
A control byte is required with most commands (see Table 25).
Table 25. Step 1 2 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1] I2C-bus byte I2C-bus start slave address for write SA6 0 3 Co 0 4 SA5 1 RS 0 SA4 1 0 0 SA3 1 0 0 SA2 0 0 0 SA1 1 0 0 SA0 0 0 0 R/W Ack 0 0 0 0 Ack 1 selects 1-line display and VLCD = VA; SCL pulse during acknowledge cycle starts execution of instruction turns on display and cursor; entire display shows character 20h (blank in ASCII-like character sets) sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted control byte sets RS for the following data bytes Display Operation initialized; no display appears during the acknowledge cycle SDA is pulled down by the PCF2113x
send a control byte for `function set'
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1
5
display control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 1 1 0 1
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Table 25. Step 7 8
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1] ...continued I2C-bus byte I2C-bus start slave address for write SA6 0 SA5 1 RS 1 SA4 1 0 0 SA3 1 0 0 SA2 0 0 0 SA1 1 0 0 SA0 0 0 0 R/W Ack 0 0 0 1 Ack 1 P writes `P'; the DDRAM is selected at power-up; the cursor is incremented by 1 and shifted to the right writes `H' PH writes `ILIP' writes `S' PHILIPS PHILIPS 0 I2C-bus 0 1 1 1 1 0 : : `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 I2C-bus 1 0 0 1 Display Operation to write data to DDRAM, RS must be set to 1 so a control byte is needed
9
send a control byte for `write data' Co 0
10
`write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1
11
`write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0
12 to 15 16
17 18
stop) (optional write (as step 8) control byte Co 1 RS 0 0 0 0 0
start + slave address for
0 0
0 0
0 0
0 0
Ack 1
PHILIPS sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR)
19
return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS SA4 1 SA3 1 SA2 0 SA1 1 SA0 0 R/W Ack 1 1 PHILIPS PHILIPS
20 21
I2C-bus start slave address for read SA6 0 SA5 1
during the acknowledge cycle the content of DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed, so the content of the DR was unknown; the R/W has to be set to 1 while still in the I2C-bus write mode DDRAM content is read from the following instructions
22
control byte for read Co 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS
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Table 25. Step 23
Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS) [1] ...continued I2C-bus byte `read data': 8 x SCL + master acknowledge [2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0 PHILIPS Display Operation 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface 8 x SCL; code of letter `H' is read first; during master acknowledge, code of `I' is loaded into the I2C-bus interface no master acknowledge; -after the content of the I2C-bus interface register is shifted out no internal action is performed; -no new data is loaded into the interface register; -data register is not updated; -address counter is not incremented and cursor is not shifted
24
`read data': 8 x SCL + master acknowledge [2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS PHILIPS
25
`read data': 8 x SCL + master acknowledge [2] DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1
26
[1] [2]
I2C-bus stop
X = not relevant.
PHILIPS
SDA is left at high-impedance by the microcontroller during the read acknowledge.
Table 26. Step 1 2 3 4 5 6 7 8 RS
Initialization by instruction, 8-bit interface [1] Description : : : : 0 0 1 1 : : 0 0 1 1 : : 1 1 : : : X X X X function set (interface is 8 bit long). BF cannot be checked before this instruction BF can be checked after the following instructions; when BF is not checked the waiting time between instructions is the specified instruction time (see Table 10) 0 1 M 0 0 0 H 0 function set (interface is 8 bit long); specify the number of display lines display off
(c) NXP B.V. 2008. All rights reserved.
Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 internal reset wait 2 ms 0 0
starting from power-on or unknown state
X
X
X
X
function set (interface is 8 bit long). Busy Flag (BF) cannot be checked before this instruction
wait 2 ms 0 0
X
X
X
X
function set (interface is 8 bit long). BF cannot be checked before this instruction
wait more than 40 s 0 0 0 0
9 10
0 0
0 0
0 0
0 0
1 0
1 0
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Table 26. Step 11 12 13
[1]
Initialization by instruction, 8-bit interface [1] ...continued Description 0 0 0 0 0 0 0 0 : 0 0 0 1 0 I/D 1 S clear display entry mode set R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
Instruction RS 0 0
initialization ends
X = not relevant.
Table 27. Step 1 2 3 4 5 6 7 8
Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation Description : : : : DB7 0 DB6 0 : : DB7 0 DB6 0 : : DB6 0 : : DB5 1 DB4 1 BF cannot be checked before this instruction function set (interface is 8 bit long) BF can be checked after the following instructions; when BF is not checked the waiting time between instructions is the specified instruction time (see Table 10) DB5 1 1 0 0 0 0 0 0 I/D DB4 0 0 H 0 0 0 1 0 S entry mode set clear display display off function set (set interface to 4 bit long) interface is 8 bit long function set (interface is 4 bit long) specify number of display lines DB5 1 DB4 1 BF cannot be checked before this instruction function set (interface is 8 bit long) DB5 1 DB4 1 BF cannot be checked before this instruction function set (interface is 8 bit long) starting from power-on or unknown state
Instruction internal reset wait 2 ms RS 0 R/W 0
wait 2 ms RS 0 R/W 0
wait more than 40 s RS 0 R/W 0 DB7 0
9 10 11 12 13
RS 0 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0 0
DB7 0 0 0 0 1 0 0 0 0
DB6 0 0 M 0 0 0 0 0 1 :
14
initialization ends
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17. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Fig 39. Package outline SOT407-1 (LQFP100)
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18. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
19. Packing information
x
A
C
y D
B F
E
mgu206
Fig 40. Tray details Table 28. Symbol A B C D E F x y Tray dimensions (see Figure 40) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 6.35 mm 5.59 mm 3.82 mm 3.66 mm 50.8 mm 50.8 mm 7 8
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PCF2113x
mgu207
Fig 41. Tray alignment
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram (Figure 3) for the orientation and position of the type name on the die surface.
20. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
20.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
20.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.
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Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
20.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 20.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 42) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 29 and 30
Table 29. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 235 220 350 220 220
Package thickness (mm)
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Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 260 250 245 > 2000 260 245 245
Table 30.
Package thickness (mm)
< 1.6 1.6 to 2.5 > 2.5
260 260 250
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 42.
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 42. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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21. Revision history
Table 31. Revision history Release date 20080304 Data sheet status Product data sheet Change notice Supersedes PCF2113_FAM_3 Document ID PCF2113_FAM_4 Modifications:
* * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Figure 3, Figure 13, Figure 20 and Figure 21: new graphics. Table 2 added: marking codes table. Table 4: adjusted die size. Table 18 and Table 19: adjusted values. Table 25: changed byte settings. Product specification Preliminary data sheet Preliminary specification PCF2113_FAM_2 PCF2113_FAM_1 -
PCF2113_FAM_3 (9397 750 06995) PCF2113_FAM_2 (9397 750 01753) PCF2113_FAM_1
20011219 19970404 19961021
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22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
63 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
24. Contents
1 2 3 4 5 6 7 7.1 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.7 9.8 9.9 9.10 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . 10 LCD supply voltage generator . . . . . . . . . . . . 10 LCD bias voltage generator . . . . . . . . . . . . . . 10 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Busy flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address counter . . . . . . . . . . . . . . . . . . . . . . . 12 Display data RAM . . . . . . . . . . . . . . . . . . . . . . 12 Character generator ROM . . . . . . . . . . . . . . . 13 Character generator RAM. . . . . . . . . . . . . . . . 18 Cursor control circuit. . . . . . . . . . . . . . . . . . . . 18 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 19 LCD row and column drivers . . . . . . . . . . . . . 19 Power-down mode . . . . . . . . . . . . . . . . . . . . . 23 Reset function. . . . . . . . . . . . . . . . . . . . . . . . . 23 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clear display . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Return home. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Entry mode set . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit I/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Display control (and partial Power-down mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Cursor or display shift . . . . . . . . . . . . . . . . . . . 29 Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bit DL (parallel mode only) . . . . . . . . . . . . . . . 29 Bit M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bit SL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bit H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Set CGRAM address . . . . . . . . . . . . . . . . . . . 29 Set DDRAM address . . . . . . . . . . . . . . . . . . . 30 Read busy flag and read address. . . . . . . . . . 30 Write data to CGRAM or DDRAM. . . . . . . . . . 30 9.11 10 10.1 10.2 10.3 10.4 10.5 10.6 10.6.1 10.7 10.7.1 10.8 10.8.1 10.8.2 10.9 10.10 10.10.1 10.11 11 11.1 11.2 11.2.1 11.2.2 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 16.6 17 18 19 20 20.1 20.2 20.3 20.4 Read data from CGRAM or DDRAM . . . . . . . Extended function set instructions and features . . . . . . . . . . . . . . . . . . . . . . . . . . . New instructions. . . . . . . . . . . . . . . . . . . . . . . Icon control. . . . . . . . . . . . . . . . . . . . . . . . . . . Bit IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit IB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct mode . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage multiplier control . . . . . . . . . . . . . . . . Bits S1 and S0 . . . . . . . . . . . . . . . . . . . . . . . . Screen configuration . . . . . . . . . . . . . . . . . . . Bit L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display configuration . . . . . . . . . . . . . . . . . . . Bit P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature control . . . . . . . . . . . . . . . . . . . . Set VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLCD programming . . . . . . . . . . . . . . . . . . . . . Reducing current consumption . . . . . . . . . . . Interfaces to microcontroller . . . . . . . . . . . . . Parallel interface. . . . . . . . . . . . . . . . . . . . . . . I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Application diagrams . . . . . . . . . . . . . . . . . . . General application information . . . . . . . . . . . 4-bit operation, 1-line display using internal reset . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit operation, 1-line display using internal reset . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit operation, 2-line display . . . . . . . . . . . . . I2C-bus operation, 1-line display . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 30 31 31 31 32 32 33 33 33 33 33 34 34 34 35 35 35 35 36 36 37 38 40 41 42 43 45 47 47 49 49 49 52 53 57 58 58 59 59 59 60 60
continued >>
PCF2113_FAM_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 4 March 2008
64 of 65
NXP Semiconductors
PCF2113x
LCD controllers/drivers
62 63 63 63 63 63 63 64
21 22 22.1 22.2 22.3 22.4 23 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 March 2008 Document identifier: PCF2113_FAM_4

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